# Maintainer: Filipe Laíns (FFY00) <lains@archlinux.org>

pkgname=vtr
_pkgname=vtr-verilog-to-routing
pkgver=8.0.0
pkgrel=4
pkgdesc='Verilog to Routing -- Open Source CAD Flow for FPGA Research'
arch=(loong64 x86_64)
url='https://verilogtorouting.org'
license=('MIT')
depends=('ctags' 'tbb')
makedepends=('cmake')
source=("$pkgname-$pkgver::https://github.com/verilog-to-routing/vtr-verilog-to-routing/archive/v$pkgver.tar.gz"
         vtr-tbb-2021.patch
         vtr-gcc11.patch
         https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ea49c34f.patch)
sha512sums=('9fc75f8451185fef65b01d37bafcc8c13e04632cdb66d0d49df7f942b40b8178a1e4610b83b88eb32b48077eeda4bd0061b8bb390e61573a1d85153fdc7ba1de'
            'f2f063b7bbb2201ca61791c86aa33de9e7d04f474b6344ac28996af61afed432fc957c452998ae8c688177634dd46e15d4e6f261572890975dfcf239f4c8ab25'
            '0fb17c1912533763f5f9338cada6315df7198c5c3992bf966c768e5fa96d74d9e1c3cec4327a636ee11e0eefe328c01f96377efb68b85253b926050511843314'
            '8ea64218b0c85b301bbfde263cdabfefc8f6ba53bc4d63664b31f5fd07c2d158296855731b321e456fa6e2df16c1859ed331c5a7d3ea6fe2e069854535babcdc')

prepare() {
  patch -d $_pkgname-$pkgver -p1 < vtr-tbb-2021.patch # Fix build with TBB 2021 (cmake config taken from prusa-slicer)
  patch -d $_pkgname-$pkgver -p1 < ea49c34f.patch # Fix build with GCC 11
  patch -d $_pkgname-$pkgver -p1 < vtr-gcc11.patch # Fix build with GCC 11
  rm $_pkgname-$pkgver/cmake/modules/FindTBB.cmake # Use upstream cmake module
  rm $_pkgname-$pkgver/libs/EXTERNAL/libtatum/cmake/modules/FindTBB.cmake
}

build() {
  mkdir $_pkgname-$pkgver/build
  cd $_pkgname-$pkgver/build

  cmake .. \
    -DCMAKE_INSTALL_PREFIX=/usr \
    -DCMAKE_BUILD_TYPE=Release

  make
}

package() {
  cd $_pkgname-$pkgver/build

  make DESTDIR="$pkgdir" install

  rm "$pkgdir"/usr/bin/*.a "$pkgdir"/usr/bin/test_* "$pkgdir"/usr/bin/*_test

  install -Dm 644 ../LICENSE.md "$pkgdir"/usr/share/licenses/$pkgname/LICENSE
}

